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ASIC Design Verification Engineer

Cisco Systems, Inc.
paid time off
United States, California, San Jose
170 W Tasman Dr (Show on map)
Dec 21, 2024

The application window is expected to close on 1/10/2025

This is an onsite role and will require working out of the Milpitas/San Jose office location.

Who We Are:

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web-scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry.

Who You'll Work With:

You will be in the Silicon One development organization as an ASIC design verification engineer in San Jose, CA. You collaborate closely with verification engineers, designers, hardware and cross-functional teams to verify the ASIC in simulation, in emulation, and during ASIC bring-up.

What You'll Do:

  • Maintaining existing DV environments and enhancing them
  • Construct testbench including scoreboard, agents, sequencers, and monitors for new blocks
  • Write test plan, develop testcases, debug regression failures and drive to module verification closure
  • Ensuring complete verification coverage through implementation and review of code and functional coverage

Minimum Qualifications:

  • Bachelor's or Master's degree and 8 years of relevant experience required; prior experience with System Verilog and UVM methodology
  • Prior experience in verifying complex blocks, clusters and top level for SoC
  • Prior experience building testbenches from scratch, hands on experience with System Verilog constraints, structures and classes.
  • Prior experience with functional coverage and constrained random DV environments.
  • Scripting skills: Perl and/or Python scripting

Preferred Qualifications:

  • Strong domain experience on one or more protocols in a plus - PCIe, CXL, Ethernet, AHB/AXI, DDR, MMU.
  • Experience with Veloce/HAPS is a plus
  • Formal verification (iev/vc formal) knowledge is a plus

#WeAreCisco

#WeAreCisco where every individual brings their unique skills and perspectives together to pursue our purpose of powering an inclusive future for all.

Our passion is connection-we celebrate our employees' diverse set of backgrounds and focus on unlocking potential. Cisconians often experience one company, many careers where learning and development are encouraged and supported at every stage. Our technology, tools, and culture pioneered hybrid work trends, allowing all to not only give their best, but be their best.

We understand our outstanding opportunity to bring communities together and at the heart of that is our people. One-third of Cisconians collaborate in our 30 employee resource organizations, called Inclusive Communities, to connect, foster belonging, learn to be informed allies, and make a difference. Dedicated paid time off to volunteer-80 hours each year-allows us to give back to causes we are passionate about, and nearly 86% do!

Our purpose, driven by our people, is what makes us the worldwide leader in technology that powers the internet. Helping our customers reimagine their applications, secure their enterprise, transform their infrastructure, and meet their sustainability goals is what we do best. We ensure that every step we take is a step towards a more inclusive future for all. Take your next step and be you, with us!

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