FE Signoff Engineer

About this opportunity:

FE Sign-Off Engineer

We are looking for an experienced Verification Engineer to help develop a Gate Level Simulation methodology as a template for organizations across the company. You would work with top experts in the GLS, develop scalable GLS methodology and make significant contribution to the overall success of many upcoming ASICs that are key to the success of the company. You will learn and work on the most up to date methods to make GLS both easier, and more effective at finding the bugs that matter.

You will:
* Drive strategic technical leadership.
* Perform the Gate Level Simulations through-out the chip development phase and as a last check before is taped-out.
* Assess the quality of the design to function in silicon, and be willing to communicate this to high levels of management.
* Perform continuous analysis and requirement handling.
* Drive continuous improvements in GLS process and methodology.
* Develop competence in technical domain.
* Work on Functional GLS and collaborate with DFX team for DFX related GLS activities.
* Additional responsibilities that can be added to this role would include multitude of formal checks on RTL (CDC/RDC analysis on Functional & DFX modes, Power/UPF constraints & validation, Timing Constraints/Exception Validation, Logical Equivalence etc.)

The skills you bring:

To be successful in the role you must have:
10 years of experience with a BSEE, or 7+ years with MSEE working at a senior level role in SOC/IP/ASIC design team with an emphasis on verification. Understanding of gate level cells and modeling required.
* Minimum Education: BSEE
* Strong debug skills and ability to work around problems
* Ability to work & communicate with EDA vendors to root-cause and drive solution for any tool related issues
* Strong prioritization skills and willingness to make hard choices
* Understanding of Simulation tools and how to maximize their performance.
* Knowledge of UVM verification methodology, assertions based verification, randomization and scoreboards.
* Good knowledge of timing concepts & SDF understanding
* Good proficiency in scripting languages like Python;
* Good focus on automation & infrastructure to enable efficient execution of GLS.
* Having good knowledge of DFX GLS activities (ATPG, MBIST, JTAG etc) is advantageous
* Understanding of Physical design implementation flows and methods to be able to assess the most likely places bugs can enter a design while going through Synthesis, DFT insertion, Place and Route, Timing fixes and ECO's.
* Understanding of formal verification/validation tools/flows is a plus (CDC/RDC, Timing Constraint/Exception Verification, UPF Validation etc.)

What happens once you apply? To prepare yourself for the next steps, please explore here: https://www.ericsson.com/en/careers/job-opportunities/hiring-process