DSP Architecture Engineer

Marvell Semiconductor, Inc.
paid time off, flex time, 401(k)
United States, California, Santa Clara
5488 Marvell Lane (Show on map)
Dec 20, 2024
About Marvell Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities. At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead. Your Team, Your Impact Marvell CE DSP Team develops and designs a variety of low power and high-speed Serializer-Deserializer (SerDes) IP in advanced CMOS technologies used in many products for the hyperscale cloud data center for AI applications. You will join a team of expert DSP mixed-signal engineers developing high-density I/O interfaces for 200G+ data rates. The candidate will also have an opportunity to experience work in industry, broaden the knowledge of key aspects of serial communication links. What You Can Expect Collaborate with analog and digital team to understand architecture and implementation constraints. Create DSP and FEC hardware block specifications appropriate for RTL implementation. Work with digital team/firmware team to implement DSP algorithm in hardware/firmware. Hands-on involvement in post-silicon performance tuning and optimization. Provide guidance on test plans for lab characterization. Provide support for internal/external customers deploying SerDes IPs. What We're Looking For Minimum Qualifications: Master's degree and/or PhD in Computer Science, Electrical Engineering, or related fields with 3-5 years of experience with DSP architectures and algorithm development. Preferred Qualifications: Deep understanding of digital communication and signal processing theory, including channel equalization, timing recovery, detection, and estimation Good programming skills in C/C++, Python or MATLAB Experience with FEC (RS, BCH, soft decoding) is a plus Experience with modelling of single ended signaling and/or DDR5 is a plus Work experience with high-speed SerDes (NRZ, PAM4) and understanding of analog circuit is a plus Team player who is willing to take on a variety of projects, and self-motivated. Expected Base Pay Range (USD) 128,160 - 192,000, $ per annum The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions. Additional Compensation and Benefit Elements At Marvell, we offer a total compensation package with a base, bonus and equity.Health and financial wellbeing are part of the package. That means flexible time off, 401k, plus a year-end shutdown, floating holidays, paid time off to volunteer. Have a question about our benefits packages - health or financial? Ask your recruiter during the interview process. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status. Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com. #LI-TT1