CPU Silicon Timing Correlation Engineer

Apple, Inc.
United States, Texas, Austin
April 24, 2024
Summary Posted: Dec 14, 2022 Role Number: 200450056 Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! In this highly visible role, you will be at the center of a chip design effort interfacing with many disciplines, with a critical impact on getting functional products to millions of customers quickly. You will be a member of a silicon timing characterization team. In this highly cross disciplinary role you will execute tasks that contribute to debugging physical issues in silicon and correlating silicon timing behavior with pre-silicon models. Key Qualifications Minimum BS and 3+ years of relevant industry experience Good all round hardware and data analysis skills Good understanding of VLSI design practice and static timing analysis Data analysis skills and experience using Python/JMP Understanding of SoC/CPU architecture is desirable Grasp of structural test (ATPG, MBIST) methods is highly desirable Lab experience (system, board or tester platform) desired Excellent teamwork and communication. Ability to work with multiple teams in delivering a solution. Description - Create and refine methodologies for isolating and debugging timing failures in system and on tester - Develop, modify and deploy tests on silicon as part of characterization plan - Analyze silicon parametric data and correlate with empirical observations - Maintain and enhance infrastructure for capturing silicon parametric data at scale - Work with partner teams e.g. DFT, physical implementation, logic design to debug issues and enhance methodology - Improve existing silicon debug features and conceive of new ones. Education & Experience Minimum BS and 3+ years of relevant industry experience Additional Requirements Additional Requirements