Senior Design Verification Engineer
 Microsoft | |
 United States, California, Mountain View | |
 Oct 04, 2024 | |
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OverviewMicrosoft is a highly innovative company that collaborates across disciplines to produce cutting edge technology that changes our world. The Silicon Architecture and Verification team is seeking a Senior Design Verification Engineer who can work with cross-discipline teams (systems, firmware, architecture, design, validation, product engineering, ...) to develop environment and test cases to verify hardware security designs. The candidate is also passionate in developing systematic and efficient methods to detecting hardware/software vulnerabilities. Our team is involved in numerous projects within Microsoft developing custom silicon for a diverse set of systems ranging from innovative high-performance consumer products to Azure and Sphere IoT. Microsoft's mission is to empower every person and every organization on the planet to achieve more. As employees we come together with a growth mindset, innovate to empower others, and collaborate to realize our shared goals. Each day we build on our values of respect, integrity, and accountability to create a culture of inclusion where everyone can thrive at work and beyond. In alignment with our Microsoft values, we are committed to cultivating an inclusive work environment for all employees to positively impact our culture every day.
ResponsibilitiesThe Microsoft Artificial Intelligence Silicon Engineering(AISiE) team is seeking a Senior Design Verification Engineer to deliver premium-quality designs once considered impossible. We are responsible for delivering cutting-edge, custom Intellectual Property(IP) and System on Chip(SoC) designs that can perform complex and high-performance functions in an extremely efficient manner. Plan the verification of complex design Intellectual Property(IP)/ system on Chip(SoC) interacting with the architecture and design engineers to identify verification test scenarios.Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology(UVM), or formally verify designs with SystemVerilog Assertions(SVA) and industry leading formal tools.Develop tests using UVM or C/C++.Analyse and debug test failures with designers to deliver functionally correct design.Identify and write functional coverage for stimulus and corner cases.Close coverage to plug verification holes and meet tape out requirements.OtherEmbody our Culture and Values | |