New

Staff Engineer, Physical Design/Timing

Aleron
United States, Texas, Austin
Sep 08, 2025
Description We are seeking a talented Staff Physical Design Engineer to join our growing team. We are the engineers behind the world's most power-efficient microcontrollers, making it possible to create long-lasting battery-powered devices that drive the future of wearable tech, hearables, and IoT. As a Staff Engineer - Timing , you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well. Responsibilities: In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime. Own all aspects of timing convergence, including Signoff to build timing correlation, PVTRc corner definition, timing margining, extraction, signoff timing analysis, glitch noise analysis, timing ECOs and interplay and tradeoff with power. Own, define and drive constraints in collaboration with RTL and IP Vendors.Have in-depth understanding of all timing collaterals for different type of Ips, namely, hard IP, Stdcell and Memory etc. Partner with post-si bringup and testing to ensure pre-si timing correlates well to post-si. Collaborate closely with RTL designers, DFT and other stakeholders to achieve best in class PPA. Continuously improve timing analysis methodologies and scripts to enhance efficiency and flow consistency. Stay at the forefront of advancements in STA and new process nodes Job Requirements Required Skills / Qualifications: Master's Degree in Electrical or Computer Engineering Minimum of 5 years experience in timing analysis and convergence Preferred Skills / Qualifications: Proven expertise in static timing analysis using industry standard timing tools like primetime (Synopsys) or tempus (Cadence). In-depth understanding of digital circuit design principles and concepts Strong proficiency with industry-standard EDA tools (e.g., Synopsys, Cadence) Excellent analytical and problem-solving skills Ability to work effectively in a team environment and communicate complex technical concepts clearly Experience with scripting languages (e.g., TCL, Python) Experience with PnR tools like Fusion Compiler (Synopsys) and Innovus (Cadence) is a plus. Aleron companies (Acara Solutions, Aleron Shared Resources, Broadleaf Results, Lume Strategies, TalentRise, Viaduct) are an Equal Opportunity Employer. Race/Color/Gender/Religion/National Origin/Disability/Veteran. Applicants for this position must be legally authorized to work in the United States. This position does not meet the employment requirements for individuals with F-1 OPT STEM work authorization status. Apply