Digital Intern - Masters Degree

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, automotive, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

ASIC design engineer responsible for the design, verification and evaluation of digital circuits in high-speed data communication ICs. The candidate will be involved in RTL design, verification, synthesis, and static timing analysis.

The responsibilities include but are not limited to:

• Work on digital design and implementation for high speed SerDes
• Write detailed digital design specifications and implement the digital design for critical timing modules
• Conduct power analysis and implement low power designs
• Support test chip/SoC integration and cooperate with AE team for silicon debug
• Support backend team with timing analysis, timing signoff, and DFT design implementation

What We're Looking For

• Enrollment in a Master degree and/or PhD program in Computer Science, Electrical Engineering or related fields, or the equivalent work experience that provides knowledge and exposure to theories, principles and concepts
• Good personal communication skills and collaborative spirit
• Strong work ethic and motivation to be part of a highly competent design team

Highly desirable skills:

• Fundamental concepts in digital design, design verification, and timing closure (STA) in support of high-speed analog mixed-signal SerDes design
• Concepts in physical and layout design
• Excellent cross-discipline communication and interpersonal skills
• Ability to work independently and as part of a team
• Strong problem-solving and decision-making skills
• Verilog coding
• Strong Perl and Tcl scripting skill
• Synthesis using Synopsys or Cadence tools
• Timing analysis using Primetime
• DFT concepts of Scan, BIST

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

As part of our commitment to fair and authentic hiring practices, we ask that candidates do not use AI tools (e.g., transcription apps, real-time answer generators like ChatGPT, CoPilot, or note-taking bots) during interviews.

Our interviews are designed to assess your personal experience, thought process, and communication skills in real-time. If a candidate uses such tools during an interview, they will be disqualified from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.