New

Analog Design Engineer (Req # KD-20260112 )

Cirrus Logic
401(k)
United States, Texas, Austin
800 West 6th Street (Show on map)
Dec 09, 2025
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn't do it without our extraordinary workforce - and that's where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! Duties Analog IP research and development including band-gap based power on reset circuits, standard cells, deglitch cells, delay macros and I/O library development; design, simulate, characterize and validate various libraries based on standard analog IP component design, as well as validation of I/O circuits, band-gap-based power on reset circuits, standard cells, de-glitch cells, delay macro's, and level shifters, both dynamic and static; transistor level design of analog IP, characterization for timing, work with layout teams to get the IP on silicon, work with design teams to define the specs for the IP, develop Verilog models for the IP, and provide guidance for integration of the IP into the chip level floorplan. Responsibilities Master of Science in Electrical, Electronics, or Computer Engineering or a closely related field plus three years of relevant experience or a Bachelor of Science in one of the foregoing fields plus five years of relevant experience, or a PhD in one of the foregoing fields without experience. The position also requires: the ability to perform transistor-level circuit simulation and design sufficient to create analog I/Os and IPs; an understanding of power and speed tradeoffs in the design of analog Ips sufficient to create analog I/Os and IPs; the ability to understand low leakage IP's to be used in mobile phone and IoT applications to design analog I/Os and IPs; an understanding of layout and the ability to guide layout engineers sufficient to design analog I/Os and IPs; proficiency with Cadence, Synopsys, or similar schematic capture, layout, and simulation tools sufficient to design analog IPs. Subject to applicable requirements, Cirrus Logic employee benefits include group health insurance and Progyny fertility coverage, other voluntary insurance options and discounts, an Employee Assistance program (EAP), 401k matching, discretionary bonus and profit-sharing programs, discretionary stock option program, access to the on-site health clinic, and hybrid work arrangements. Cirrus Logic International Semiconductor Ltd is an Equal Opportunity/Affirmative Action Employer. We strive to select the best qualified applicant for any opening and to reward employees based on their skills, experience and performance. We do not discriminate on the basis of race, national origin, pregnancy status, marital status, gender, age, religion, physical or mental disability, medical condition, veteran status, sexual orientation, genetic information or any other characteristic protected by law. Export control restrictions based upon applicable laws and regulations would prohibit candidates who are nationals of certain embargoed countries from working in this position without Cirrus Logic first obtaining an export license. Candidates for this role must be able to access technical data without a requirement for an export license. We are unable to sponsor or obtain export licenses for this role. Cirrus Logic strives to select the best qualified applicant for any opening. Different approaches, ideas and points of view are both valued and respected. Employment decisions are made on the basis of job-related criteria without regard to race, color, religion, sex, national origin, age, protected veteran or disabled status, genetic information, or any other classification protected by applicable law.