Staff Engineer, AI/ML for Circuit Design

Our team is at the forefront of applying machine learning to real-world chip design for OLED display applications. As part of a dynamic group of researchers, engineers, you will collaborate on innovative projects that transform data into insights and breakthrough discoveries of new circuits with high performance for next-generation displays.

Samsung Display Lab is hiring an AI expert with background in circuit/pixel layout design, placement and routing in circuits, parasitic capacitance extraction, and circuit evaluation by fusing physics-based methods with modern AI/ML methods. You will drive AI-assisted panel layout and architect pixel/backplane circuits, including placement and routing, build high-fidelity surrogates for parasitic capacitance prediction, and optimization of panel layout area. As an EDA engineer, you will support the development, verification, and optimization of pixel circuits for advanced displays (OLED, micro-LED, etc).

Location: Daily onsite presence at our San Jose, CA office / U.S. headquarters in alignment with our Flexible Work policy.

What You'll Do

• Develop EDA design workflows for pixel circuits for OLEDs
• Create automatic scripts for schematic generation and layout assembly
• Apply Reinforcement Learning and/or Diffusion models for placement and routing (P&R) and compare their efficacy with classical P&R algorithms
• Build AI-based surrogate models for parasitic capacitance extraction
• Apply Graph Neural Networks (GNN) for circuit design and/or surrogate models for circuit parameters estimation
• Apply design of experiments (DoE) and optimization methods to accelerate simulation and parameter tuning
• Develop optimization algorithms for pixel array compaction
• Contribute to continuous improvement of model accuracy through active learning and uncertainty analysis

What You Bring

• BS Computer Science or equivalent with a minimum of 5+ years or a MS in Computer Science with 3+ years or PhD 0+ years in Electrical Engineering/Computer Engineering/Applied Physics (or equivalent experience)
• Proficiency with SPICE/Spectre/HSPICE/Cadence Virtuoso/ADE; layout and parasitic extraction
• Strong Python and ML fundamentals (PyTorch or TensorFlow, scikit-learn/NumPy/Pandas)
• Experience building and validating surrogate models and running multi-objective optimization
• Experience with Reinforcement Learning (RL), Diffusion models, and Graph Neural Networks (GNN)
• Experience with Cadence Innovus, Synopsys Fusion Compiler, Aprisa, GDSFactory, KLayout is a plus
• Hands-on experience with EDA tools for layout assembly, placement and routing, parasitic capacitance extraction, pixel circuit area compaction, etc.
• Knowledge of classical algorithms for placement and routing in chip design
• Publications/patents in display, EDA, or ML-for-hardware
• Solid analog/digital circuit fundamentals; hands-on OLED pixel/gate driver design
• You're inclusive, adapting your style to the situation and diverse global norms of our people
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding
• You're collaborative, building relationships, humbly offering support and openly welcoming approaches
• Innovative and creative, you proactively explore new ideas and adapt quickly to change

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