Senior Staff Engineer, Digital Verification

The ACD Design verification team independently verifies the ASIC designs against standardspecifications. This gives an unbiased view of ASICs as compared to the design engineers. Thishelps the designs to stick to standard specifications and helps in detection of bugs in early stages of the design cycle and saves engineering costs. The ACD Design Verification team verifies the ASICs targeted for designs of GNSS Location, Cellular modem RF and High-Speed interface. You will get an opportunity to work cutting edge technologies and contribute to the cutting-edge products designed by Samsung for great customer experiences. You will get involved in ASIC verification of the designs targeted for the wearables and handsets and you will be designing the test benches at the block level, SoC level and helping in verification closures.

Daily onsite presence at our San Jose or San Diego office in alignment with our Flexible Work policy

What You'll Do

• Collaborate with RTL Designers, System Architects to define verification specifications.
• Design the test suites for full chip and block level verification, develop direct and constrained random testcases, analyze and debug simulations at RTL and Gate level.
• Build the functional coverage models, collect and analyze coverage data.
• Build test benches for Low Power designs, analyze simulations with Hybrid UPF and PG netlists.
• Manage regression analysis, file and track bugs using bug tracking systems.

What You Bring

• Bachelors with 15+ years of relevant industry experience, or Masters with 13+ years or PhD with 10+ years in Electrical Engineering or related field preferred.
• Experience in developing test benches using SystemVerilog UVM, testcase development skills for constrained random and directed scenarios.
• Experience in MCU/CPU Verification at processor level and at sub-system level both.
  
  
  
  1. Strong understanding of CPU architectures, instruction sets (x86, ARM, RISC-V flavors).
  2. Core architecture/micro-architecture verification
  3. Multi-processor Cache (L2/L3) Coherency, Memory Hierarchy Verification
  
  
  
  

• Good object-oriented programming skills in C++/SV, scripting languages like Python/Perl.
• Familiarity with Formal Verification.
• DMS Verification experience or knowledge preferred.
• You're inclusive, adapting your style to the situation and diverse global norms of our people.
• An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
• You're collaborative, building relationships, humbly offering support and openly welcoming approaches.
• Innovative and creative, you proactively explore new ideas and adapt quickly to change.

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