Senior ASIC RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE:

As a member of the SBIO frontend design and integration team, you will collaborate with architecture, IP design, physical design, and product engineering teams to develop and deliver highquality IP for SOC products. In this role, you will contribute to design, integration, documentation, and crossfunctional coordination to help achieve firstpass silicon success.

THE PERSON:

We welcome applicants with experience in digital design, processor architecture, and verification who enjoy solving complex technical challenges. Ideal candidates communicate clearly, work effectively in crosssite or distributed teams, and are comfortable learning new skills as technologies evolve.

KEY RESPONSIBLITIES:

• Design RTL for highspeed digital blocks, including clock, reset, and powerrelated features.
• Architect and implement powermanagement features and lowpower RTL techniques.
• Integrate IP blocks at the subsystem level and resolve interIP design and integration issues.
• Manage clockdomain crossing and linting activities for IP and subsystem designs.
• Collaborate with FEINT, DFT, Physical Design, and SOC teams to incorporate feedback across disciplines.
• Contribute to architecture, microarchitecture, and design documentation.
• Provide clear status updates and participate in teambased problemsolving activities.

PREFERRED EXPERIENCE:

• Background in digital IP/ASIC design and Verilogbased RTL development.
• Familiarity with the full IP design cycle, including requirements, architecture, verification, and validation.
• Understanding of RTL verification, designquality checks, synthesis, timing closure, and postsilicon validation.
• Experience with frontend EDA tools, signoff flows, and lowpower design methodologies.
• Working knowledge of scripting languages such as Python or Perl.
• Ability to collaborate effectively on crossfunctional teams and manage multiple technical tasks.
• Ability to create clear technical documentation in English.
• Understanding of semiconductor engineering terminology and digital design concepts.
• Knowledge of or experience with functional design verification.

ACADEMIC CREDENTIALS:

• Bachelors or Master's degree in computer engineering/Electrical Engineering orequivalent field of study.

This role is not eligible for visa sponsorship.

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.