ASIC Design Engineer: DFT-IP

About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

What You Can Expect

• Understanding and driving design requirements to meet customer specifications
• Pick up and run the defined computer-aided design (CAD) tools/flow for the assigned designs
• Design and Develop the SOC using Linux. TCL, Python/Perl (or other equivalent scripting languages)
• Analyze, debug, and implement DFT features using defined CAD tools/flow
• IEEE 1687 JTAG ATE test development for AMS IP
• Simulation/Verification of ATE test suite at IP, Block, and Top-level netlist
• Collaborate with global CAD teams on design flow fixes and feature improvements
• Define and implement test strategy for complex mixed-signal circuit designs
• Interlock across the entire design team to drive solutions and resolve problems
• Provide debug and support manufacturing test team during hardware bring-up
• Developing specifications and design documentation
• Excellent communication skills and ability to work within a tightly-coupled team are a must

What We're Looking For

• Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 15+ years of related professional experience.
• Master's degree and/or PhD in Computer Engineering, Electrical Engineering or related fields with 15+ years of experience.
• Language Fluency - Fluent in English Language - written & verbal.

Expected Base Pay Range (USD)

The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.