Design Verification Engineer

In-Person Interview Required

Design Verification Engineer
Minneapolis, MN
9 + Months

Role:
Full DV ownership of a custom 36 I/O die-to-die PHY test chip from planning to tape-out.

What You'll Do:
Build UVM/SystemVerilog testbenches from scratch.
Verify custom blocks: Eye Monitor, PRBS Error Counter, and I2C Interface.
Implement SVA and Formal Verification (JasperGold/VC Formal).
Manage regressions and provide post-silicon bring-up support.

What You Bring:
BS/MS/PhD in EE, CE, or related field.
6-12 years of UVM/SystemVerilog experience.
At least 1 complete tape-out in a primary/lead DV role.
Experience verifying serial management interfaces (I2C, SPI, APB).

Dexian stands at the forefront of Talent + Technology solutions with a presence spanning more than 70 locations worldwide and a team exceeding 10,000 professionals. As one of the largest technology and professional staffing companies and one of the largest minority-owned staffing companies in the United States, Dexian combines over 30 years of industry expertise with cutting-edge technologies to deliver comprehensive global services and support.

Dexian connects the right talent and the right technology with the right organizations to deliver trajectory-changing results that help everyone achieve their ambitions and goals.To learn more, please visit https://dexian.com/.

Dexian is an Equal Opportunity Employer that recruits and hires qualified candidates without regard to race, religion, sex, sexual orientation, gender identity, age, national origin, ancestry, citizenship, disability, or veteran status.