Interconnect Micro-architect/RTL Design Engineer

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At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

The Role:
As a member of the Infinity Fabric Architecture and RTL team,you will design and implement key components of a scalable, coherent on-chip network that enables high-speed communication across CPUs, GPUs, and accelerators. This role focuses on defining microarchitecture and developing RTL for interconnect (NoC/fabric) subsystems that support a wide range of products including servers, AI platforms, client devices, and gaming systems. You will work closely with cross-functional teams across Austin and global sites to deliver high-quality, performance-optimized hardware in a collaborative, fast-paced environment.

The Person:

Key Responsibilities:

• Define microarchitecture for interconnect (fabric / network-on-chip) components
• Develop and implement synthesizable RTL using Verilog/SystemVerilog
• Optimize designs to meet power, performance, area, and timing goals
• Contribute to scalable, coherent interconnect solutions across multiple product lines
• Collaborate with architecture, verification, and cross-functional engineering teams
• Support unit-level validation and deliver high-quality RTL to verification teams
• Develop assertions and contribute to coverage strategies
• Debug design issues during pre-silicon and post-silicon phases
• Create clear and maintainable design documentation

Preferred Experience:

• Experience with RTL design using Verilog or SystemVerilog
• Background in interconnect, network-on-chip (NoC), or cache/memory subsystem design
• Understanding of processor architecture, including coherency and memory systems
• Knowledge of digital design fundamentals and high-speed hardware systems
• Experience debugging RTL or hardware systems
• Familiarity with power, performance, and area tradeoffs
• Exposure to scripting or programming languages such as Python, C, or C++
• Awareness of design-for-test (DFT) concepts
• Familiarity with x86 or ARM architectures is helpful
• Interest in using AI-assisted tools to improve design and debugging workflows

Academic Credentials:

BS, MS, or PhD degree in Electrical or Computer engineering preferred.

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AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.

AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.

This posting is for an existing vacancy.