ASIC Physical Design, Sr Manager-17107

At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation.

You Are:

You are an accomplished ASIC Physical Design leader with a passion for developing cutting-edge silicon solutions and building high-performing teams. With 15+ years of progressive experience in VLSI and ASIC design, you possess a deep technical understanding of front-end and back-end processes, including RTL, verification, synthesis, and advanced node physical implementation (2nm, 3nm, 4nm, 5nm, 7nm). You thrive in dynamic, fast-paced environments and excel at leading cross-functional teams to deliver complex projects on schedule. Your hands-on expertise is matched by your strategic vision, enabling you to drive technical innovation while managing resources, budgets, and stakeholder expectations.

What You'll Be Doing:

• Leading the end-to-end physical implementation of test chips across multiple advanced foundry nodes (2nm-7nm), ensuring timely and high-quality project delivery.
• Managing, mentoring, and developing a multidisciplinary team of ASIC physical design engineers, fostering a culture of technical excellence and collaboration.
• Collaborating with cross-functional teams-including front-end design, verification, and product engineering-to drive seamless project execution from RTL to GDSII.
• Overseeing project planning, resource allocation, and team budgeting to align with organizational goals and customer requirements.
• Interfacing directly with customers and stakeholders to gather requirements, provide status updates, and ensure satisfaction throughout the project lifecycle.
• Driving continuous process improvement, leveraging your expertise in Synopsys EDA tools to optimize design flows and achieve best-in-class PPA and sign-off metrics.
• Ensuring compliance with industry standards and best practices for design closure, static timing analysis (STA), and sign-off methodologies.

What You'll Need:

• 15+ years of experience in ASIC physical design, with a proven track record of successful project delivery at advanced technology nodes (2nm-7nm).
• Strong hands-on expertise in front-end (RTL, verification, synthesis) and back-end (physical implementation, STA, PPA optimization) design flows.
• Demonstrated leadership in managing, mentoring, and developing high-performing engineering teams.
• Proficiency with Synopsys EDA tools and methodologies, including tool flow optimization and sign-off processes.
• Experience in project management, team budgeting, resource planning, and stakeholder engagement.
• Excellent communication, presentation, and interpersonal skills for effective collaboration with internal and external partners.

The Impact You Will Have:

• Championing the successful delivery of complex, high-performance ASIC designs that enable Synopsys and our customers to lead in the competitive semiconductor industry.
• Shaping the technical direction and best practices for physical design implementation across multiple programs and advanced technology nodes.
• Enhancing team capabilities through mentorship, training, and fostering a culture of innovation and continuous improvement.
• Building and maintaining strong relationships with customers, ensuring their requirements are met and exceeding expectations for quality and delivery.
• Driving operational excellence by optimizing design methodologies, tool flows, and resource utilization for maximum efficiency.
• Contributing to Synopsys' reputation as a global leader in EDA and semiconductor solutions by delivering projects that set industry benchmarks.

Who You Are:

• Strategic thinker with strong problem-solving skills and a bias for action.
• Collaborative and inclusive leader who values diverse perspectives and empowers team growth.
• Adaptable and resilient in the face of challenges, with a continuous learning mindset.
• Customer-focused, with a commitment to delivering high-quality solutions that meet and exceed expectations.
• Highly organized, detail-oriented, and able to manage multiple priorities in a fast-paced environment.

The Team You'll Be A Part Of:

You will be joining a high-impact, innovative team of physical design engineers at Synopsys' Bangalore site. The team is dedicated to delivering state-of-the-art ASIC solutions for leading global customers, working closely with cross-functional groups and leveraging the latest EDA technologies. As a leader, you will play a key role in shaping the team's technical direction, fostering collaboration, and driving excellence in every project.

#L1-NK4

At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability.

In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S.